The present invention relates to an automatic wiring method for a semi-custom semiconductor circuit device and, more particularly, to a computer-aided automatic wiring pattern design method for forming wiring paths between a plurality of function circuit blocks selected to obtain a desired LSI circuit function on a chip substrate in accordance with a predetermined routing scheme.
Unlike a full-custom LSI (large-scale integrated circuit), the importance of a semi-custom LSI has recently increased for semiconductor manufacturers because of its short development period, superior flexibility for realizing various LSI specifications, and relatively low manufacturing cost. A building block type or general cell type LSI is a typical semi-custom LSI wherein a plurality of selected function circuit blocks (which are also called "modules") such as a CPU (central processing unit), an ALU (arithmetic logic unit), a PLA (programmable logic array), a RAM (random access memory), a ROM (read only memory), or a polycell unit are discretely arranged on a semiconductor chip substrate. A proper wiring pattern consisting of partial lines (trunks) which run along the row and column directions (X and Y directions) of the substrate is added in a substrate wiring region defined to surround these function blocks, and an electrical wiring is performed between function blocks for desired functions.
Conventionally, according to the semi-custom LSI of this type, a computer-aided routing design method may be adopted to determine the wiring pattern for electrical connections between the above function blocks. For example, when a channel wiring method is adopted to design the above wiring pattern, a wiring region is divided into a plurality of sub-wiring regions (which are known as "channels" to those skilled in the art) so as to correspond to the function blocks arranged on the substrate. Since each function block generally has a rectangular shape on the substrate, each sub-wiring region, i.e. channel, is defined to have a flat rectangular shape so as to be located adjacent to the corresponding function block. Therefore, adjacent channel regions on the substrate contact each other through a linear boundary. The allowable number of wires (tracks) extending along the row and column directions, which can be formed in each channel, is determined in correspondence to the surface area of each channel. In order to satisfy the above requirement for track numbers and simultaneously to minimize the length of each wire, the wiring pattern required to realize the desired LSI functions is determined independently for each channel.
For example, a wiring pattern in a channel between a function block and other associated function blocks is designed in such a manner that terminals of the function block are correctly connected to the corresponding terminals of the associated function blocks. In this case, the allowable track number in the above channel is normally taken into consideration, and each connection wire is constituted by a plurality of partial lines extending along the row and column directions. The row and column lines are respectively formed in two conductive layers stacked to be electrically insulated from each other, and connections at necessary positions therebetween are performed through contact holes. When determination of the wiring pattern in one channel is completed, a wiring pattern of another channel adjacent thereto is then determined in the same manner.
According to the conventional automatic wiring design method described above, however, it is very difficult to improve packing density of the resultant semi-custom LSI to a desired extent. This is because an independent wiring pattern in each channel region is simply repeatedly designed so that wiring density in the channel largely varies for each channel region, resulting in a non-effective use of the channel region. In the LSI thus obtained, if a space which does not contribute at all to wiring pattern formation (and which tends to be formed often especially at portions where channels contact each other) is left in the channel region, packing density of the LSI is naturally reduced.